Projects 2009

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Date	Name	Description	Experiment
February	VUPROM3	Redesign of VUPROM2 (error correction)	HY-PHI
July	FEBTESA1	FEBEX1 to LEMO input Adapter	any
July	PEXOR2	Redesign with Lattice SCM40 FPGA	any
July	VULOM5	VME Logic Module redesign with VIRTEX5 (30,50,85,110)	any
July	TRIXOR1	PCI based trigger module driven by PEXOR module	any
August	EXPLODER1	LVDS to Optical Link Interface	R3B, HADES
August	FEBEX1	8 channel 12 bit 65 MHz Sampling ADC Board	R3B, PANDA
August	FEBTESA1	Test adapter for FEBEX (LEMO connectors)	tests
August	VULOM5_AD1	VULOM5 adapter with 4 x multi gigabit optical transceivers	any
August	PRA-AD2	Preamplifier differential to single ended adapter	TASCA
September	LEVCON1	Universal Level Converter NIM, TTL, ECL, LVDS, PECL, RS485	any
September	APFADA1	FEBEX to APFEL Adapter	any
October	VULOM4	Redesign of VULOM3 (IC delivery discontinuity)	any
November	PEXOR3	Redesign of PEXOR2 (error correction)	PANDA, SHIP
December	FEETEX1 GET4-EXPLODER	EXPLODER1 Interface for GET4 TDC